Culloden, 1746: Battlefield Guide by Stuart Reid

By Stuart Reid

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Currently the main products are the Xtensa 6 and Xtensa LX processor templates. The former is targeted for low-power, the latter for high-end applications. For example, the Xtensa 6 template is a 32bit architecture and consists of a 5-stage pipeline with alternatively 16-bit or 24-bit instructions. User defined registers and execution data paths may have a width of up to 1024 bits. Several additional units such as memory blocks, MMU, multiply and MAC units are optional and/or configurable. The extensions are defined using the TIE (Tensilica Instruction Extension) Language.

The IP library contains switches, width converters, endianness converters, long distance links containing repeaters, as well as different NoC interface units (NIUs) for the communication end points. Via the NIUs, local buses like AMBA can be connected (GALS, Globally Asynchronous Locally Synchronous communication). Alternatively, cores can be directly connected using AHB, AXI or OCP communication protocols. The Arteris NOC Solution consists of the Danube IP Library together with a suite of design tools, namely the NOCexplorer and the NOCcompiler.

1), basic decisions about the NoC communication architecture are made. These decisions concern (a) the basic properties of communication modules to use, as well as (b) their optimal interconnect topology. For these examinations, no architecture specific simulators are necessary yet. Ideally, for this Architect’s View (AV) use case, generic communication models are applied, which are combined to a generic parameterizable Network-on-Chip model. 1 1 NoC Channel ... M S 1 ... 3. NoC Channel Overview 30 Communication Modeling In the context of this book, the AVF performance simulation environment has been used [73, 1].

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